Yatish Turakhia

Yatish Turakhia

Conferences

  1. Y. Turakhia*, S. D. Goenka*, G. Bejerano, W. Dally, “ Darwin-WGA: A Co-processor Provides Increased Sensitivity in Whole Genome Alignments with High Speedup” , International Symposium on High-Performance Computer Architecture (HPCA), 2019. [paper, slides, code]

  2. Y. Turakhia, G. Bejerano, W. Dally, “Darwin: A Genomic Co-processor Provides 15,000× Speedup on long read assembly”, Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2018 (Best paper award). [paper, slides, code]

  3. Y. Turakhia, B. Raghunathan, S. Garg, D. Marculescu, “HaDeS: Architectural Synthesis for Heterogeneous Dark Silicon Chip Multi-processors”, Design Automation Conference (DAC), 2013. [paper, slides]

  4. B. Raghunathan, Y. Turakhia, S. Garg, D. Marculescu, “Cherry-Picking: Exploiting Process Variations in Dark-Silicon Homogeneous Chip Multi-Processors”, Design, Automation, and Test in Europe Conference (DATE), 2013. [paper, slides]

Journals

  1. Y. Turakhia*, H. I. Chen*, A. Marcovitz*, G. Bejerano, “A fully-automated method discovers loss of mouse-lethal and human-monogenic disease genes in 58 mammals”, Nucleic Acids Research (NAR), Jul 2020 [paper, code].

  2. W. Dally, Y. Turakhia, S. Han, “Domain-Specific Hardware Accelerators”, Communications of the ACM (CACM), Jul 2020 (cover page article) [paper].

  3. A. Marcovitz*, Y. Turakhia*, H. I. Chen*, M. Gloudemans, B. A. Braun, H. Wang, G. Bejerano, “A functional enrichment test for molecular convergent evolution finds a clear protein-coding signal in echolocating bats and whales”, Proceedings of the National Academy of Sciences of the United States of America (PNAS), Oct 2019. [paper, code]

  4. Y. Turakhia, G. Bejerano, W. Dally, “Darwin: A Genomic Co-processor”, IEEE Micro (Top Picks), May 2019. [paper]

  5. Y. Turakhia, G. Liu, S. Garg, D. Marculescu, “Thread Progress Equalization: Dynamically Adaptive Power-Constrained Performance Optimization of Multi-threaded Applications”, Transactions on Computers (TC), Apr 2017. [paper]

Book Chapters

  1. S. Garg, Y. Turakhia, D. Marculescu, “Heterogeneous Dark Silicon Chip Multi-Processors Design and Run-time Management”, The Dark Side of Silicon (Energy Efficient Computing in the Dark Silicon Era), Springer, 2016. [chapter]

Pre-prints

  1. Y. Turakhia*, B. Thornlow*, L. Gozashti, A. S. Hinrichs, J. D. Fernandes, D. Haussler, R. Corbett-Detig, “Stability of SARS-CoV-2 Phylogenies”, bioRxiv preprint, Jun 2020. [pre-print, code]

  2. J. Schull*, Y. Turakhia*, W. Dally, G. Bejerano, “Champagne: Whole-genome phylogenomic character matrix method places Myomorpha basal in Rodentia”, bioRxiv preprint, Oct 2019. [pre-print]

  3. Y. Turakhia, S. Das, T. Aamodt, W. Dally, “HoLiSwap: Reducing Wire Energy in L1 Caches”, arXiv preprint, Jan 2017. [pre-print]

Workshop papers

  1. R. Snytsar, Y. Turakhia, “Parallel approach to sliding window sums”, International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP), 2019. [paper]

  2. V. Kumar, P. Engineer, M. Datar, Y. Turakhia, S. Agarwal, S. Diwale and S. Patkar, “Framework for Application Mapping over Packet-switched Network of FPGAs : Case studies”, FPGAs for Software Programmers Workshop (FPL) at the International Conference on Field Programmable Logic and Applications, 2015. [paper]

Patents

  1. Y. Turakhia, J. Jaffari, A. Panda, K. Chatha, “An Architecture for Sparse Neural Network Acceleration”, US Patent App. 15/393,670 (Pending).

  2. Y. Turakhia, J. Jaffari, A. Panda, K. Chatha, “A Low Power Architecture for Sparse Neural Network”, US Patent App. 15/377,858 (Pending).

(* implies authors made equal contributions)